Today, a receiving section and a transmitting section in communication equipment, such as cell phones or wireless LANs, are configured so as to be powered down to save power when communications are not conducted, and so as to be turned on only when transmission and reception are performed. Therefore, semiconductor circuits, such as communication equipment of this type, have a problem in that if it takes time to recover from a power down state to an operational state, a latency time occurs before communications are started.
According to a conventional technique, in a circuit whose circuit characteristics are greatly degraded when noise is mixed with a reference voltage, a stabilizing capacitor is connected to stabilize the reference voltage and thereby reduce the effects of the noise. However, in order for the circuit having such a stabilizing capacitor to recover from a power down state to an operational state, the stabilizing capacitor needs to be charged to a desired reference voltage. A rapid recovery circuit is used to shorten this charging time. However, if the rapid recovery circuit does not turn off in the vicinity of the desired voltage, it will take time for the circuit to settle after the rapid recovery circuit turns off, and the recovery time cannot be reduced further.
Hereinafter, an example of a conventional rapid recovery circuit will be described with reference to FIG. 16.
In FIG. 16, the reference numeral 90 refers to a rapid recovery circuit; 1 to a comparator; 2 to a stabilizing capacitor; 3 to a switch composed of a p-type transistor; ref 1 to a first comparator threshold voltage (from on to off); ref 2 to a second comparator threshold voltage (from off to on); vin to a comparator input; out1 to a first comparator output; Vbias to a reference voltage; I1 to a current source; Ia to a first current path in a semiconductor circuit (not shown), such as communication equipment, to which the reference voltage Vbias is supplied; Ib to a second current path in the semiconductor circuit; and AVDD to a power supply voltage. It is assumed that the first current path Ia and the second current path Ib are the sum total of the current paths connected with the reference voltage Vbias in the circuit. In FIG. 17, the reference characters Vb denote a reference voltage final value, and the reference character T indicates a charging completion time.
In order to reduce effects of noise and the like, the stabilizing capacitor 2 is connected between the reference voltage Vbias and the power supply voltage AVDD. When the semiconductor circuit is in the power down state, the reference voltage Vbias is fixed at the power supply voltage AVDD. Therefore, in order for the semiconductor circuit to recover from the power down state to the normal operational state, the stabilizing capacitor 2 needs to be charged from the power supply voltage AVDD to the reference voltage final value Vb as shown in FIG. 17.
For the purpose of reducing this charging time, the rapid recovery circuit which charges the stabilizing capacitor 2 at a high speed by using the current source I1 is provided. When the semiconductor circuit recovers from the power down state, the current source I1 is turned on by the switch 3, which is controlled by the comparator 1, and charges the stabilizing capacitor 2. As shown in FIG. 17, when the reference voltage Vbias becomes the first comparator threshold voltage ref1 by charging the stabilizing capacitor 2, the comparator 1 turns off the switch 3 to stop the charging by the current source I1. Thereafter, the first current path Ia or the second current path Ib in the semiconductor circuit performs charging or discharging, so that the reference voltage Vbias is stabilized at the reference voltage final value Vb.
Therefore, the charging completion time T of the stabilizing capacitor 2 is obtained as the sum total of the time during which charging is performed by the rapid recovery circuit 90 and the time elapsed between the point at which the rapid recovery circuit 90 starts the OFF operation and the point at which the reference voltage Vbias is stabilized at the reference voltage final value Vb by the first current path Ia or the second current path Ib.
Another configuration for such a rapid recovery circuit is described in Patent Document 1, for example.
Patent Document 1: Japanese Laid-Open Publication No. 2004-280805 (FIG. 5)